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Freescale Semiconductor /MK61F15WS /DDR /CR20

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Interpret as CR20

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00)LPRE 0RESERVED0CKSRE0RESERVED 0CKSRX0RESERVED 0 (WRMD)WRMD 0RESERVED

LPRE=00

Description

DDR Control Register 20

Fields

LPRE

Low Power Refresh enable

0 (00): Refreshes occur

1 (01): Refreshes do not occur

2 (10): Reserved

3 (11): Reserved
RESERVED

Reserved
CKSRE

no description available
RESERVED

Reserved
CKSRX

Clock Self Refresh Exit
RESERVED

Reserved
WRMD

Write Mode Register
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data